Part one of this article described the problem, showed the impact of a cold start test pulse on an automotive power supply and discussed a typical pre-booster specification. This second part provides guidance on proper part selection of all relevant components. It also shows the reaction of a pre-booster on a cold crank test pulse and the impact of its error amplifier. By Matthias Ulmann, Texas Instruments.
General part selection
Figure 3 - pre-booster schematic
Several components of the booster have an influence on achieving stable output voltage on a test pulse applied to the input. Let’s walk through the single components and their selection.
The boost controller itself is supplied by its own output voltage. By doing this, the internal bias voltage is always on its nominal level of 8.0V and a no logic level FET for the power stage is needed. Besides that it offers the possibility to use the boost converter with input voltages below the minimum supply voltage of the IC.
Reaction of a booster on a test pulse
Figure 4 shows the waveforms of a typical pre-booster working in CCM during a test pulse. The green waveform is the input voltage, which follows the pulse described in Figure 1. Red is the voltage on the input capacitor behind the reverse polarity protection diode. The purple waveform is the output voltage of the booster and dark blue the inductor current with a significant elevation at first. The output of the boost controller’s error amplifier COMP is represented by the light blue trace on the bottom.
Figure 4 - complete cold start test pulse "severe" applied to a pre-booster
The purple boost output voltage shows a significant dip right at the beginning of the test pulse when the battery voltage drops from 11.0V down to 3.2V. After this event the output voltage is stable and well-regulated at 9.0V. So the most critical point for a pre-booster is to handle this large voltage drop without there being too large an impact and drop of the output voltage. The rest of the test pulse is pretty easy to handle and basically just a matter of thermal design. A closer look at the critical part of the test pulse is shown in Figure 5.
Figure 5 - beginning of the cold start test pulse "severe" applied to a pre-booster
The falling input slope is damped by the input capacitor (green trace). It takes approximately 1.2ms until the booster starts switching and the inductor current rises. Up to this point, the load is supplied only by the output capacitor and the output voltage is ramping down. Then the converter output starts to recover and settles at the nominal voltage of 9.0V.
In the following part we will discuss the reason for this behaviour in detail and how to improve it.
Impact of the error amplifier
The 1.2ms delay of the booster right at the beginning is caused by the saturation of the error amplifiers output (COMP). With 11.0V at the input the voltage on the feedback resistor divider is higher than the reference voltage. Thus the voltage at the error amplifier goes down to zero volts and the converter won’t switch. When the test pulse is applied, the output voltage drops and the feedback voltage goes below the reference voltage. Then the error amplifier needs to charge the capacitors of the compensation network (capacitors between COMP and FB / Pin 4 and 5) to a certain value needed for regulation. But the charge current is limited by the maximum output current of the error amplifier (250µA typical) and the resistor in series to the larger capacitor. This delay caused by the saturation of the error amplifier has the biggest impact on the breakdown of the output voltage during a cold start test pulse. The only way to mitigate this problem is to reduce the value of the capacitors and increase the resistor’s value. But this is not possible as these three components set the gain, one zero and one pole for the error amplifier to provide a well-regulated output, fast load regulation, as well as enough phase and gain margin. The bandwidth and therefore the gain of a booster working in CCM is practically limited by the right half plane zero. For a stable and reliable design, the maximum bandwidth is somewhere between one tenth and one fifth of this frequency.
The formula shows that the only possibility to influence this right half plane zero is the inductance, as all other parameters like output voltage, load current and duty cycle are given by the specification of the booster. When designing the compensation network it is important to consider the lowest frequency of the right half plane zero which occurs at the lowest input voltage and the maximum load. The bandwidth of such a pre-booster is typically in the range of some hundreds of Hertz up to several Kilohertz. Now, these conditions limit the bandwidth and result in specific values for the compensation network which cannot just be changed for improved test pulse behaviour without the risk of getting unstable over lifetime. A high bandwidth means large resistor and small capacitors in the compensation network, so the only way for a booster in CCM is to shift the right half plane zero to high frequencies by reducing the inductance. Then the output of the error amplifier can charge the capacitors faster and regulation starts earlier when a test pulse is applied.
The comparison in Table 1 shows the improvement regarding output voltage regulation if the bandwidth of the pre-booster is increased. The compensation network is adjusted such that the phase and gain margin are similar (at least 60° phase and -20dB gain margin). However the bandwidth is virtually doubled. Unless otherwise specified, all following measurements use a “standard” test setup. It uses an input capacitance of 220µF, an inductance of 2.2µH, an output capacitance of 47µF and the output voltage is set to 9.0V. The output is loaded with 10W by a LM53602-Q1 synchronous buck converter providing 5.0V at 2.0A.
Table 1 - doubling the bandwidth
With the bandwidth doubled, the breakdown of the output voltage is 26 percent compared to 58 percent with the lower bandwidth. The minimum voltage of 6.7V is well above the 5.0V output voltage of the subsequent buck converter and the system will work continuously and without interruption.
It brings a clear benefit to push the bandwidth of the pre-booster as high as possible, but sufficient phase and gain margin is still needed. Decreasing the inductance and thereby pushing the right half plane zero to higher frequencies offers potentially higher bandwidths and lower breakdown of the output voltage. Another benefit is the slightly lower inductor peak current. To understand this, a closer look at the output capacitor can help. While the input voltage is falling and the converter is not yet switching, the load is solely supplied by the output capacitor. As soon as the booster is switching, it needs to supply not only the load current, but also recharge the output capacitor. The lower the bandwidth, the higher the regulation delay, the higher the discharge of the capacitor and, as a consequence, the higher the current needed to recharge it.
The final part demonstrates the differences between operation modes and the influence of the inductance and capacitance on performance. Read part 3.