DSP implemented in next-generation ADAS chip

13th June 2019
Posted By : Mick Elliott

To meet functional safety requirements, Toshiba has implemented the Cadence Tensilica Vision P6 DSPs for its next-generation automotive SoC. The Vision P6 DSP provides high compute throughput with low power consumption, small core area and a strong partner ecosystem, and is certified to meet functional safety requirements.

Offering up to 3.8X more power efficiency than CPUs alone and 1024 giga-operations (GOPS) of processing power, the Vision P6 DSP serves as a powerful offload engine, efficiently processing vision and AI workloads to meet the demands for accurate detection and identification of objects.

Toshiba has integrated the Cadence Xtensa Imaging Library (Xi-Lib) into its software development kit (SDK), enabling its customers to easily access the Vision P6 DSP to execute custom algorithms, further strengthening its SDK offering.

Using the Xi-Lib allowed Toshiba to easily port their existing vision algorithms to run on the DSP, reducing development time and effort.

In addition, the Vision P6 DSP core, development tools and libraries are all designed to enable SoC vendors to achieve ISO 26262 automotive safety integrity level D (ASIL D) certification.

The Vision P6 DSP also supports AI applications developed in the Caffe and TensorFlow frameworks through the Tensilica Neural Network Compiler (XNNC).

The compiler maps neural networks (NNs) into executable and highly optimised high-performance code for the Vision P6 DSP, leveraging a comprehensive set of optimised neural network library functions from the Tensilica NN library.

It also supports the Android Neural Network (ANN) API for on-device AI acceleration in Android-powered devices. The Vision P6 DSP has been integrated in top-tier mobile phone application processors, surveillance camera processors and AR/VR processors.


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