Enhanced test platform centre stage in Stuttgart

4th May 2018
Posted By : Mick Elliott
Enhanced test platform centre stage in Stuttgart

Modern vehicles can contain up to 50 microprocessors embedded within systems that range from engine control and ABS to climate control and instrument display panels. Since the consequences of failure can, in some cases, be catastrophic the requirements for assembly quality and subsequent reliability are paramount.

JTAG Technologies will use the platform of the Automotive Test Expo in Stuttgart (June 5-7) to show products that are used to detect faulty products the world over, in automotive component factories building ECUs, NightVision systems, Airbag controls, Telematics modules etc.

These systems have tested boards and programmed devices in hundreds of thousands of vehicles used both on and offroads in every continent.

Among the products on show is the latest version of the JTAG Visualizer

It allows users to assess fault coverage data and pin-point production test faults in a snap.

Users can import schematic data direct from Mentor (Pads, DxDesigner, Capture) Cadence Altium and Zuken tools as well as board layout information in ODB++ and a dozen other vendor specific formats.

Alsi introduced in this version of Visualizer is a Maps feature that offers a basic test-accessibility view by a simple click of the mouse.

The view can easily be fine-tuned by adding just a few key component descriptions to a look up table.

Using customisable colours to indicate test coverage levels or access types, a color-coded schematic can be displayed or printed.

While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote 'kernel-centric' testing.

Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can 'bridge' from the JTAG interface to the resources of the gate array itself.

The CoreCommander FPGA product implements a 'translator' interface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone, CoreConnect Avalon etc.).


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