Cadence Design Systems

Address:
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RG12 OPH
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Phone: +44.1344.360333

Fax: + 44.1344.869647

Web: www.cadence.com


Cadence Design Systems articles

Displaying 1 - 20 of 26

Memory IP subsystem wins ISO 26262 ASIL C certification

Good news for Cadence Design Systems is that its LPDDR4/4X memory IP subsystem, utilising TSMC’s 16nm FinFET Compact (16FFC) technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for advanced driver assistance systems (ADAS) and L3/L4 autonomous driving applications.
23rd April 2019

DSPs achieve ISO 26262 ASIL D compliance

Products in the Cadence Tensilica functional safety portfolio and its design processes have achieved certification of ISO 26262 compliance up to ASIL D for the development of automotive applications. The Tensilica products and processors offer the broadest range of ISO 26262-compliant processors and DSPs and continue to expand across vision, AI, radar, lidar, sensor fusion, wireless/wired communication, audio/voice processing and highly optimised controller applications.
1st March 2019

embedded world: DSP lifts radar/lidar and 5G performance

embedded world: DSP lifts radar/lidar and 5G performance
Boosting performance by up to 10X for Automotive Radar/Lidar and up to 30X for 5G communications the Cadence Tensilica ConnX B20 DSP IP becomes the highest-performing DSP in the ConnX family. Based on a deeper processor pipeline architecture, this DSP provides a faster and more power-efficient solution for the automotive and 5G communications markets, including next-generation radar, lidar, vehicle-to-everything (V2X), user equipment (UE)/infrastructure and IoT applications.
26th February 2019


On-device applications covered by DNA AI processor

On-device applications covered by DNA AI processor
The Cadence Tensilica DNA 100 Processor IP, deep neural-network accelerator (DNA) AI processor IP delivers high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs. As a result, the DNA 100 processor is well suited for on-device neural network inference applications spanning autonomous vehicles (AVs), ADAS, surveillance, robotics, drones, augmented reality (AR) /virtual reality (VR), smartphones, smart home and IoT.
21st September 2018

Automotive solution for safety verification to achieve certification

Automotive solution for safety verification to achieve certification
Cadence Design Systems has announced that its Cadence Automotive Solution has been used by ROHM for safety verification, a critical component of its ISO 26262-compliant tool chain for automotive LSIs. The ROHM flow, which has achieved ASIL D certification from TÜV Rheinland, which utilises Cadence fault injection simulation technology, and can reduce the effort required to complete the safety verification process by up to 50% for automotive applications.
13th July 2018

Automotive smart viewing camera processor selected by GEO

Cadence Design Systems has announced that GEO Semiconductor selected the Cadence Tensilica Vision P5 DSP for GEO’s new GW5400 camera video processor. According to GEO, their GW5400 is the world’s first automotive smart viewing processor.
27th February 2018

Automotive design solutions on show at embedded world 2018

Automotive design solutions on show at embedded world 2018
At embedded world 2018 Cadence Design Systems will showcase its latest Cadence Tensilica DSPs and design tools targeted for automotive applications. The demonstrations will take place in hall 4/4-116 at the Exhibition Centre in Nuremberg, Germany from 26th February to 1st March 2018, where the theme of the event is 'Automotive Electronics Redefined'.
13th February 2018

Design flows receive 'Fit for Purpose - TCL1' certification

Design flows receive 'Fit for Purpose - TCL1' certification
Cadence Design Systems has announced that it has achieved the industry’s first comprehensive 'Fit for Purpose - Tool Confidence Level 1 (TCL1)' certification from TÜV SÜD, enabling automotive semiconductor manufacturers, OEMs and component suppliers to meet stringent ISO 26262 automotive safety requirements. To achieve certification, Cadence provided its tool and flow documentation to TÜV SÜD for evaluation, and TÜV SÜD confirmed the Cadence flows are fit for use with ASIL A through ASIL D automotive design projects.
12th October 2017

IP portfolio for automotive design enablement platform

IP portfolio for automotive design enablement platform
A comprehensive automotive IP portfolio for the TSMC 16nm FinFET Compact (16FFC) automotive process technology has been delivered by Cadence Design Systems. This broad IP portfolio enables a host of applications ranging from in-vehicle infotainment, in-cabin electronics, vision subsystems, digital noise reduction and advanced driver assistance system (ADAS) subsystems and is registered in the TSMC9000A programme.
13th September 2017

Verification solution adopted for automotive IC development flow

Verification solution adopted for automotive IC development flow
Cadence Design Systems has announced that the Cadence Functional Safety Verification Solution was adopted by ROHM CO in its design flow for ISO 26262-compliant ICs and LSIs for the automotive market. The Cadence fault simulation technology and seamless reuse of functional and mixed-signal verification environments enables an ISO 26262-compliant development flow that can reduce the effort required to complete the safety verification process up to 50%.
20th July 2017

Collaboration accelerates development of automotive applications

Collaboration accelerates development of automotive applications
In order to port the AUTOSAR-compliant TOPPERS ATK2-SC1 (Toyohashi OPen Platform for Embedded Real-time Systems Automotive Kernel version-2 Scalability Class 1) to Cadence Tensilica processors and DSPs, Cadence Design Systems has collaborated with the embedded real time System Laboratory of Nagoya University. Nagoya University and Cadence jointly ported the ATK2-SC1 to the Tensilica processor platform, validating that it functions correctly and operates at competitive performance levels.
12th July 2017

Automotive IP and design solutions displayed at embedded world

At embedded world 2017, Cadence Design Systems will showcase its latest Tensilica DSPs and design tools targeted for automotive applications. The demonstrations will take place in Hall 4/4-116 at the Exhibition Centre in Nuremberg, Germany from March 14th-16th 2017, where the theme of the event is 'Automotive Electronics Redefined.' The Cadence automotive-themed demonstrations will highlight the following:
10th March 2017

PSpice integration with MATLAB and Simulink improves productivity

Cadence Design Systems has announced it has partnered with MathWorks to streamline system-level design and circuit-level implementation for mixed-signal internet of things (IoT) and automotive applications.
7th November 2016

IP solutions address requirements for ADAS

Cadence Design Systems has announced a broad portfolio of Cadence interface and Denali memory IP solutions for automotive applications supporting TSMC’s 16nm FinFET Compact (16FFC) process. By offering a wide array of IP using TSMC’s 16FFC process, Cadence is enabling automotive customers to accelerate time to market while gaining the benefits of TSMC’s most advanced process technology used in automotive applications.
23rd September 2016

Open standards to improve automotive Ethernet

Open standards to improve automotive Ethernet
A team at Cadence Design Systems take a closer look at the new open standards being developed to improve the reliability and redundancy of automotive Ethernet. Ethernet is the key technology to enable advanced driver assistance systems (ADAS) and autonomous driving, owing to its low cost, low weight, high data rate and non-proprietary nature. 
29th June 2016

Simulation tools adopted for automotive designs

Following an extensive evaluation process, Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs. The evaluation process gave Cypress the opportunity to dramatically improve its turnaround time and productivity with the Cadence solution when compared with its previous flow.
11th May 2016

Build the car of the future today at embedded world

At embedded world 2015, Cadence Design Systems will demonstrate its latest solutions for ADAS, infotainment, ECU design, automotive Ethernet, early software development and verification of embedded systems. In particular, the company will showcase its Tensilica infotainment solutions and Protium rapid prototyping platform, as well as functional safety and security verification, automotive Ethernet/ADAS, embedded system verification and debugging, and IC package and PCB design and analysis.
11th February 2015

Safety verification reduces ISO 26262 compliance preparation by 50%

Claimed to reduce the effort required by automotive designers to prepare for ISO 26262 compliance by up to 50%, Cadence Design Systems has introduced an automotive functional safety verification solution. The fault injection and safety verification technologies, which help automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level, are an expansion to the company’s Incisive functional verification platform.
24th October 2014

Cadence and QNX Announce New Tensilica HiFi Audio/Voice DSP Application for In-Car Active Noise Control

Cadence Design Systems, Inc announced that QNX has ported its QNX Acoustics for Active Noise Control (ANC) software to the Cadence Tensilica HiFi Audio/Voice digital signal processing (DSP) core. The Tensilica HiFi Audio/Voice DSP from Cadence is available immediately. 
26th June 2014

CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems

Cadence Design Systems Inc announced that CSR plc selected the Cadence Palladium XP verification computing platform for system and early firmware validation of ARM-based automotive infotainment systems-on-chip (SoCs). Using Palladium Hybrid technology, CSR experienced a 200X speed-up for OS bringup, which shaved months off the development cycle. 
19th June 2014


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