new IAR KickStart Kit provides all of the hardware, software and tools to develop an embedded application around Toshiba’s new TMPM350FDFTG microcontroller. This ARM-based device has been specifically designed to meet the needs of electric power steering control applications.
Operating at up to 88MHz, the TMP350FDFTG combines an ARM Cortex-M3 CPU core with 512KB of embedded NANO Flash™ ROM and 48KB of RAM. An integrated dual channel CAN controller (VER. 2.0B) and advanced motor control circuitry minimise the need for external components, while on-board fault supervisors simplify compliance with ISO 26262. The result is a device that provides a single-chip solution for both control and functional safety.
The IAR TMPM350FDFTG KickStart Kit comprises a microcontroller evaluation board, IAR’s visualSTATE® graphical design environment and the IAR Embedded Workbench® integrated development environment (IDE) for ARM-based processors. A J-Link hardware debug probe that connects via USB to a host PC provides JTAG debugging functionality in accordance with ARM specifications. Full documentation and example application code are also provided within the kit.
In addition to the microcontroller, the kit’s evaluation board provides a JTAG connector for programming/debugging, CAN, USB, RS232 and UART connectivity, a power jack and four user-programmable buttons. The board also incorporates eight user LEDs, a potentiometer input analogue signal and two on-board crystal oscillators.
IAR visualSTATE allows developers to represent any complex reactive system with UML state machines, which is particularly beneficial for control logic-based applications where reliability, size and deterministic execution are key criteria. The Embedded Workbench IDE provides a complete and easy-to-use set of C/C++ cross compiler and debugger tools and is fully integrated with the J-Link debug probe.
The TMPM350FDFTG provides functional safety compliance in accordance with ISO 26262 through a distributed safety architecture built around tightly coupled fault supervisors. These supervisors run algorithms that monitor the operation of each of the MCU’s functional blocks using efficient faultRobust (fR) blocks of safety IP implemented close to key functions such as the CPU, buses, timers and memory*. An fRNET block collects diagnostic information from each individual function while Toshiba hardware diagnostic (ThwD) blocks provide further safety monitoring. The new IAR KickStart is provided with the necessary software code to initialise this on-board safety structure.
* fRCPU, fRBUS, fRMEM and fRNET blocks comprise third party IP developed by Toshiba partner Yogitech.