Denso Gains Significant Productivity and Quality-of-Results Advantages with Cadence Mixed-Signal, Low-Power Solutions

“In the highly competitive automotive electronics market, reliability is a must,” said Yoichi Oishi, manager of the Electronics Device Business Unit at Denso during his recent speech at the CDNLive! Japan technical conference. “We needed to revamp our design tools so we could develop chips more efficiently without compromising on quality. After adopting the Cadence Encounter and Virtuoso flows, we achieved our goals in terms of chip quality and time to market.”

To achieve improved power, performance and area on the digital parts of advanced node designs, Denso used the Encounter RTL-to-GDSII flow, which includes Encounter RTL Compiler for global synthesis and the Encounter Digital Implementation System for design implementation. For the analog sections, Denso deployed Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment in a complete custom/analog flow from spec-driven multi-test environment with sensitivity analysis and circuit parameter optimization for robust, centered designs through full custom layout.

For in-design and signoff extraction, Denso used Cadence QRC Extraction, which is tightly integrated into the Virtuoso and Encounter flows for faster convergence and time to market. By switching QRC Extraction from another vendor’s technology, Denso was able to eliminate the file interface and directly manage data from Virtuoso environment, resulting in a productivity boost and faster time to market.

“Cadence provides customers like Denso with a complete mixed-signal and low-power design solution—one that can help them improve key metrics such as power, performance and area,” said Qi Wang, group director, Solutions Marketing at Cadence. “Whether they are working at advanced nodes or mainstream geometries, design teams are incorporating Cadence flows to meet ambitious business and market objectives.”